Verilog Input Text Parsing using Python Regex -

so i'm trying parse verilog files using python. need find inputs, outputs, etc. however, in files, inputs , outputs have multiple bitwidths, so:

input read_enable, input [width-1 : 0] write_data,

i'm using regular expressions go through text file 1 line @ time, right if line contains word input run:

input_mod = re.search(r'(.*?)input\s(.*?)(\s?)(.*?),', line) inputs.append(input_mod.group(4))

where inputs list declared earlier. need extract input's name. i'm rather new python , regex's i'm not sure if work, correct? there better way this?

note: know doxygen exists, boss wants native function in python class.

.*?\binput\b.*? (\s+),

you can use this.inputs.append(input_mod.group(1))this take care of in between input , last non space string before ,.see demo.

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