Best way to modify strings in VHDL -

i'm writing test bench vhdl design made , need write message text file. message of format

[instance_name];[simulation_time]  

(i.e. u0;700 ns) , filename must [instance_name].log. getting instance name , simulation time no problem, writing custom filename has been problematic. under simulation, instance name given in format:

"u0\componentx\test\"  

and replace slashes underscores. there easy way this?

our poc library has quite big collection on string operations/functions. there str_replace function in poc.strings should solve question. there poc.utils package non string related functions, helpful in handling strings , file i/o.

a simple implementation:

function replace(str : string) return string   variable result : string(str'range) := str; begin   in str'range loop     if (result(i) = '\')       result(i)  := '_';     end if;   loop;   return result; end function; 

usage:

constant original : string := "u0\componentx\test\"; constant replaced : string := replace(original);