hdl - Accessing wire/reg dimensions in Verilog -

in vhdl there many predefined attributes can in making code more generic, e.g.:

signal sig : std_logic_vector(7 downto 0);   -- ...   in sig'range loop ... 

is there similar way access dimensions of verilog wire or reg?

of course it's possible define boundaries of each wire or reg parameter in:

parameter w_upper = 7;   parameter w_lower = 0;   wire [w_upper:w_lower] w;  

but seems lot of overhead , far less elegant vhdl.

i have seen systemverilog has things $bits, $size, $high , $low, verilog-2005 or earlier?

verilog-2005 doesn't have equivalents vhdl attributes ('size, 'left, 'right, 'high, 'low, etc.).

as mentioned in question, feature introduced in systemverilog, have following attributes: $dimensions, $unpacked_dimensions, $left, $right, $low, $high, $increment, $size.