Verilog: generic parameters -

i have several verilog (not system-verilog) blocks want generate them depending on other parameters. example:

module some_module (in, out)  realtime p = 3.5; // parameter want change  initial begin if ('global_parameter == 1)     p = 5.8; if ('global_parameter == 2)     p = 4.4; end  core_module #(p) core (in, out); endmodule 

here, "global_parameter" defined in header file overridden @ simulation time using simulator parameters. , core module uses "p" delay value in example:

module core_module(in, out)  parameter p = 1;  out <= #p in; // p should constant  endmodule 

therefore, i'm hoping have core module updated parameter "p". scenario not simulate-able. please recommend me possible solid solution problem if possible?

thank you

a parameter needs parameter type throughout design. cannot pass variable parameter.

you can use generate block control instantiation:

module core_module#(parameter realtime p=1)(input in, output out);   @(in) out <= #(p) in; // p should constant endmodule  module some_module (input in, output out);   generate     if (global_parameter == 1) begin : cfg_1       core_module #(5.8) core (in, out);     end     else if (global_parameter == 2) begin : cfg_2       core_module #(4.4) core (in, out);     end     else begin : cfg_dflt       core_module #(3.5) core (in, out); // default     end   endgenerate endmodule 

you can calculate parameter in single line:

module some_module (input in, output out);   parameter p = (global_parameter == 1) ? 5.8 : (global_parameter == 2) ? 4.4 : 3.5;   core_module #(p) core (in, out); // default endmodule 

alternatively (since can not synthesizing), can have delay value variable, force value through hierarchical reference. example:

module core_module (input in, output out);   realtime p = 1;   @(in) out <= #(p) in; // p variable endmodule  module some_module (input in, output out);   realtime p = 3.5;   core_module core (in, out);   initial begin     if (global_parameter == 1)       p = 5.8;     else if (global_parameter == 2)       p = 4.4;     force core.p = p; // force hierarchical variable assignment   end endmodule 

_{note: example compatible ieee std 1364-2001 , ieee std 1364-2005, utilizing ansi header style , generate blocks. these features not exist in ieee std 1364-1995}

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i'm not aware of clean verilog solutions. can try embed code (such perl's ep3, ruby's eruby/ruby_it, python's prepro, etc.) mention in answer similar question, here. challenge embedded need pre-compiled/processed, making them more `define parameters.

if systemverilog option, can following: (refer ieee std 1800-2012 § 6.20 constants; example near end of § 6.20.2)

module some_module (input in, output out);   parameter realtime p [3] = '{3.5, 5.8, 4.4};   core_module #(p[global_parameter]) core (in, out); endmodule