vhdl - Reset output after run -

i'm working on small project learn vhdl. i'm working on bcd converter (converting binary bcd number).

but got stuck when implementing testbench. doesn't reset output after patterns got applied.

my vhdl code of entity:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity bcd_mod         port (                 entry: in std_logic_vector(16 downto 0);                 outp: out std_logic_vector(20 downto 0)         ); end bcd_mod;  architecture calculate of bcd_mod  begin         process(entry)                 variable outp_cp : std_logic_vector(20 downto 0) := (others => '0');                 variable place : integer := 1;                 variable digit : integer := 0;                 variable number : integer := 0;                  begin                          in 16 downto 0 loop                                 case entry(i)                                         when '0' => null;                                         when '1' => number := number + (2**i);                                         when others => null;                                 end case;                         end loop;                          if number > 99999                                 outp_cp(20) := '1';                         else                                 while (number > 0) loop                                         digit := number mod 10;                                          if place = 1                                                 outp_cp(3 downto 0) := std_logic_vector(to_unsigned(digit, 4));                                         elsif place = 2                                                 outp_cp(7 downto 4) := std_logic_vector(to_unsigned(digit, 4));                                         elsif place = 3                                                 outp_cp(11 downto 8) := std_logic_vector(to_unsigned(digit, 4));                                         elsif place = 4                                                 outp_cp(15 downto 12) := std_logic_vector(to_unsigned(digit, 4));                                         else                                                 outp_cp(19 downto 16) := std_logic_vector(to_unsigned(digit, 4));                                         end if;                                          number := number - digit;                                         number := number / 10;                                         place := place + 1;                                 end loop;                         end if;                          outp <= outp_cp;                         outp_cp := (others => '0');          end process;  end calculate; 

my testbench code:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity bcd_mod_testbench end bcd_mod_testbench;  architecture calculate of bcd_mod_testbench         component bmt                 port(entry : in std_logic_vector(16 downto 0); outp : out std_logic_vector(20 downto 0));         end component;          bmt_0: bmt use entity work.bcd_mod;                 signal entry : std_logic_vector(16 downto 0);                 signal outp : std_logic_vector(20 downto 0);                 begin          bmt_0: bmt port map (entry => entry, outp => outp);          process                 type pattern_type record                         entry : std_logic_vector(16 downto 0);                         outp : std_logic_vector(20 downto 0);                 end record;                  type pattern_array array (natural range <>) of pattern_type;                 constant patterns : pattern_array :=                 (("00000110111101101", "000000011010101100101"),                  ("00000000000000011", "000000000000000000011"),                  ("00000000000011011", "000000000000000100111"));                 begin                  in patterns'range loop                          entry <= patterns(i).entry;                          wait 1 ns;                          assert outp = patterns(i).outp                         report "wrong bcd number." severity error;                 end loop;                  assert false report "end of test." severity note;                 wait;         end process; end calculate; 

and here's output in gtkwave. can see here, after running code big number, following numbers start number before ends.

(clickable)

hope tips solve problem.

in vhdl, variable retains it's value between process re-entry. thus, when enter process number x"000003", variables still have value add @ end of processing of x"003565".

a quick test shows setting place 1 @ start of process fixes problem:

process(entry)     variable outp_cp : std_logic_vector(20 downto 0) := (others => '0');     variable place : integer := 1;     variable digit : integer := 0;     variable number : integer := 0; begin     place := 1;      ...