pipeline - Is there an execute-store data hazard in MIPS? -

on mips architecture pipelining , forwarding:

add $s0, $t1, $t2 sw $s0, 0($sp) 

the add instruction have result ready @ step 3 (execute operation) presume sw instruction want result @ step 2 (instruction decode & register read).

there solved exercise in book computer organization , design david a. patterson: find hazards in following code segment , reorder instructions avoid pipeline stalls:

lw  $t1, 0($t0) lw  $t2, 4($t0) add $t3, $t1,$t2 sw  $t3, 12($t0) lw  $t4, 8($01) add $t5, $t1,$t4 sw  $t5, 16($t0) 

solution:

lw  $t1, 0($t0) lw  $t2, 4($t1) lw  $t4, 8($01) add $t3, $t1,$t2 sw  $t3, 12($t0) add $t5, $t1,$t4 sw  $t5, 16($t0) 

in solution correctly recognizes load-use hazard , rearranges code accordingly, there execute-store hazard well?

let's consider mips in forwarding activated. think in case no hazard occurs: in fact add instruction integer operation in mips architecture requires 1 clock cycle. @ graph:

add $t3,$t1,$t2    if   id   ex   mem   wb sw  $t3,12($t0)         if   id   ex    mem  wb 

as can see no hazard occurs because sw instruction stores datum after 2 clock cycles since result put in $t3 add.

actually in similar situations hazard can occur if unit multicycle 1 (if requires more 1 clock cycle compute data). ad example, in add.d instruction uses floating point adder requires 4 clock cycles perform calculation:

add.d f2,f4,f5      if   id   a0   a1   a2   a3   mem   wb s.d   f2,somewhere       if   id   ex   x0   x1   x2    mem    wb 

x0 , x1 raw stalls while x2 structural stalls: in former case s.d must wait add.d finish; in latter mips cannot access in same clock cycle memory 2 times, structural stall occurs.